Dynamically Reconfigurable Mixed Signal System Design

Dynamically Reconfigurable Mixed Signal System Design

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In this thesis, a dynamically reconfigurable mixed signal system is designed with Field Programmable Gate Array and Field Programmable Analog Array. Signal generation and signal analysis circuits are implemented in FPGA. Circuit under test (CUT) is implemented in FPAA. Analog and digital parts are interfaced via analog to digital converter (ADC) and digital to analog converter (DAC). Analog front end with gain stage and signal conditioning circuits are also included in the design. The fault testing method in time domain is based on magnitude comparison with varying input amplitudes. In frequency domain, Fast Fourier Transform is implemented for Signal to Noise Ratio (SNR) analysis. The system is ideal for analog circuit online self-testing and self-repairing. It's also a flexible platform for ADC and DAC testing.First, 8 bit ADC samples are read in and stored in 8 bit RAM, and then gain coefficient is calculated. ... Data path includes all the digital processing units such as adders, multipliers, registers etc. ... This can be implemented in Verilog code as follows: reg [7:0] mem [127:0]; RAM controller is used to generate control signals toanbsp;...

Title:Dynamically Reconfigurable Mixed Signal System Design
Author: Rui Xiao
Publisher:ProQuest - 2007

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