Multi-Net Optimization of VLSI Interconnect

Multi-Net Optimization of VLSI Interconnect

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This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.In the previous chapters, the sizing of bundles of parallel wires has been discussed. ... The third significant difference between the bundle wires and the parallel wires in general layouts is that the wires in general layouts do not start or end atanbsp;...

Title:Multi-Net Optimization of VLSI Interconnect
Author: Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Publisher:Springer - 2014-11-07

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