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Statistical timing analysis is an area of growing importance in nanometer te- nologiesa€š as the uncertainties associated with process and environmental var- tions increasea€š and this chapter has captured some of the major efforts in this area. This remains a very active field of researcha€š and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuitsa€š a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this booka€š the reader is referred to [LNPS00a€š HN01a€š JH01a€š ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies.

Author: Sachin Sapatnekar
Publisher:Springer Science & Business Media - 2004-06-02

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